Chip storage capacity increased by 50%
Chip storage capacity increased by 50%, fifth-generation DRAM platform unveiled, ChangXin pushes DUV to its limits. ChangXin Memory Technologies (the domestic memory manufacturer that refused Apple's price cut) has made new moves again. On September 20, at the World Manufacturing Convention, ChangXin officially announced that its fifth-generation DRAM technology platform G5 has entered mass production, and also introduced two new 24Gb LPDDR5X products. The official website's exact words were: "The process level of this platform is on par with the industry's top mass-production process nodes."
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Chip storage capacity increased by 50%, fifth-generation DRAM platform unveiled, ChangXin pushes DUV to its limits. ChangXin Memory Technologies (the domestic memory manufacturer that refused Apple's
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Chip Storage Capacity Increased by 50%, Fifth-Generation DRAM Platform Exposed, ChangXin Pushes DUV to Its Limit
ChangXin Memory Technologies (the domestic memory manufacturer that refused Apple's price cut) is making moves again. On September 20, at the World Manufacturing Convention, ChangXin officially announced mass production of its fifth-generation DRAM technology platform G5, along with two new 24Gb LPDDR5X products. The official website states that "this platform's process level is on par with the industry's top mass-production process nodes."
How should this be interpreted? Let me break down the officially published parameters one by one.
First, Understanding "Half-Pitch" (3-Minute Primer)
To measure how advanced a DRAM process is, you look at the "active area half-pitch" — half the distance between the centerlines of two active areas in the memory array.
This number directly determines density: the smaller the half-pitch, the more memory cells you can fit on the same wafer, the more dies you can cut out, and the lower the cost. When memory manufacturers compete on process, this is the number they're competing over.
G5 brought this number down to 11.95 nanometers. For reference, the current advanced DRAM from Samsung, SK Hynix, and Micron is roughly in the 10nm-class range. By paper geometry, ChangXin has reached the doorstep of the first tier for the first time.
Quadruple Patterning (The Workaround When You Can't Buy EUV)
Here's the problem: the big three pushed down to the 10nm-class by relying on EUV extreme ultraviolet lithography. ChangXin can't buy EUV (ASML's EUV lithography machines are banned from sale to China) — so how did they do it?
The answer is quadruple patterning. Traditional lithography projects a circuit pattern onto the silicon wafer in one pass; DUV deep ultraviolet lithography doesn't have enough resolution, so pattern edges get blurry. So they split that layer's pattern into four sets of masks, expose four times, each time etching a portion, and finally assemble the same precision. The more exposures, the finer the dimensions achievable — but the longer the process, the harder the alignment, and the greater the yield pressure.
This is what "pushing DUV to its absolute limit" means — last year Huawei's Kirin used a similar approach to bypass EUV restrictions for logic chips, and this time ChangXin has pushed this path to 11.95 nanometers in memory.
Two accompanying breakthroughs are also worth noting: HKMG high-k metal gate process (originally a logic chip technology, now adapted to DRAM), which compressed the core functional area height to 6762 nanometers; officials also mentioned a digital twin system that runs the process through on a virtual production line before going to the real line.
45:1 and 100:1 (Where the Gap Lies)
In a DRAM cell, besides the transistor, there's a storage capacitor responsible for holding that 1 bit. If the capacitor isn't deep enough, the charge can't be stored, and data is lost. To fit the capacitor into ever-smaller cells, you can only dig deeper — the aspect ratio is the ratio of capacitor depth to width.
G5 achieved 45:1, meaning the capacitor is 45 deep and 1 wide. What does that mean? It's like digging 45 meters down into a 1-meter-wide pit, while ensuring the walls don't collapse and the bottom doesn't leak electricity.
SK Hynix has given a roadmap judgment: when DRAM critical dimensions drop below 10 nanometers, the aspect ratio needs to exceed 100:1. 45:1 is enough for this generation, but the next generation will need to double — etching, deposition, mechanical stability, every link's difficulty is rising exponentially.
The Undisclosed Yield (The Final Suspense)
After talking technology, let's pour some cold water. In this official announcement, there are several numbers the officials didn't give:
One, yield. The +50% dies per wafer is a theoretical value (converted at 8Gb dies), but how many good dies can actually be cut wasn't mentioned. Two, cost per bit. Theoretically lower, but how much it actually drops depends on yield. Three, supply schedule. Domestic media have reported that some customers can no longer get supply commitments beyond this quarter — tight capacity is a good thing, but it also shows ramp-up pressure exists.
For reference, take HBM3E: industry chain estimates put ChangXin's HBM yield at around 25%. The difficulty of quadruple patterning is different from HBM, but the pressure is equally significant.
I think Yicai's "Yi Rating" put it fairly accurately: "Theoretical process density has substantively caught up with the international first tier." Between theoretical density and actual capacity, what stands in between is precisely the yield hurdle.
What It Means for Us (At the End of the Day)
Connect ChangXin's moves over the past month: global first launch of LPDDR6 (Xiaomi 18 Fold), HBM3E trial production, G5 mass production entering flagship phones, small-volume adoption by HP, ASUS, and Acer, 200,000 wafers per month in Hefei and Beijing with a year-end push to 350,000 wafers.
Memory prices have risen for three consecutive years, 32GB kits have doubled in price, and the root cause is the big three shifting capacity to feed HBM, tightening consumer-side supply. In this situation, having one more capable supplier matters two years from now: once ChangXin's capacity ramps up, there will be one more variable in DDR5 and LPDDR5X pricing power.
The good news is the direction is right; the cold water is that yield is still unknown. During this week of celebration articles flying everywhere, I'd rather watch the next data point: when will G5 platform yield be disclosed, and what will it be when disclosed.
Chinese celebration articles say "on par with the international top tier," but calm analysis all points to the same suspense — yield. How much longer do you think domestic memory yield needs to climb? Share your judgment in the comments.
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