"CXMT 4F²: Tear Down the Transistor and Rebuild It" Voiceover Script Style: Lively with memes · Technical terms read in Chinese style (4F² → "4F squared", 6F² → "6F squared", VSG → spelled out letter by letter) Voice: Doubao TTS · zh_male_qingshuangnanda_uranus_bigtts (Fresh Male College Student) · 1.2x S1 Hook (approx. 18s) October

💡 What You Will Learn

"CXMT 4F²: Tear Down the Transistor and Rebuild It" Voiceover Script Style: Lively with memes · Technical terms read in Chinese style (4F² → "4F squared", 6F² → "6F squared", VSG → spelled out letter

📜 Table of Contents

• S1 Hook (~18s)
• S2 Understanding F and 6F² (~18s)
• S3 The Wall Has Been Reached (~16s)
• S4 Core: The Transistor Stands Up (~24s)
• S5 The 3D Route: Decoupling + Hybrid Bonding (~18s)
• S6 Product and the Deciding Move (~16s)
• S7 Closing (~10s)
• Fact Checklist (Verified, Sources: Yicai / SEMI China / Nanfang+ / Shenzhen Electronic Chamber of Commerce / Markets.com, 2026-10)

"CXMT 4F²: Tearing Down the Transistor and Rebuilding It" Voiceover Script

Style: Lively with memes · Technical terms read in Chinese (4F²→"4F squared", 6F²→"6F squared", VSG→spelled out) Voiceover: Doubao TTS · zh_male_qingshuangnanda_uranus_bigtts (Refreshing College Guy) · 1.2x

S1 Hook (~18s)

October 10th, Shanghai. CXMT President Cao Kanyu announced at a chip conference: by year's end, they'll launch a next-gen DDR5 memory using a 4F-squared architecture. When the news broke, Micron's stock dropped 3.9% that same day. Samsung and SK Hynix won't adopt this technology until 2028 — CXMT just pulled the industry's generational timeline forward by two years with a single stroke. Why does one architecture upgrade make all three memory giants tremble?

S2 Understanding F and 6F² (~18s)

To understand 4F-squared, you first need to know F. F is the minimum line width lithography can etch — essentially the smallest Lego brick. Each DRAM memory cell is one transistor plus one capacitor, responsible for storing a single 0 or 1. The industry's mainstream architecture is called 6F-squared — one cell occupies the area of six bricks. This architecture has been in use since 2007, nearly twenty years now.

S3 The Wall Has Been Reached (~16s)

For twenty years, the entire industry's playbook was just one thing: cut the bricks smaller, cram more compartments into the same plot of land. But once the walls get thin enough, you can't build anymore — any thinner, and charge leaks out like crazy. The 6F-squared path has hit its physical limit. Some analyst firms have flat-out concluded: 4F-squared is the theoretical floor for a single-bit cell. To go further, you have to tear down the house and rebuild.

S4 Core: The Transistor Stands Up (~24s)

CXMT's approach is exactly that — tear down and rebuild. Transistors used to lie flat; now they make them stand up. A person standing takes up less floor space than lying down — same principle for transistors. Cell area drops from six bricks to four, boosting density by 30% to 50% in the same footprint. Even better is CXMT's self-developed VSG transistor, where the gate wraps around the channel from all directions — leakage and short-channel effects are solved structurally, no more patching things up by raising refresh rates.

S5 The 3D Route: Decoupling + Hybrid Bonding (~18s)

Actually, 4F-squared isn't a new idea — people were tinkering with it back in the 1980s. But back then, the memory array and peripheral circuits were bound to the same process, compromising with each other, and performance was actually worse than 6F-squared — so the idea fizzled out. CXMT's solution is a 3D route: decouple the memory and logic processes, let each optimize independently, then use wafer-level hybrid bonding to connect the two sides at high speed. Like building the house and the road separately, then connecting them at the end.

S6 Product and the Deciding Move (~16s)

According to the plan, the first-generation product is a DDR5 RDIMM, aimed squarely at server memory. This territory used to belong entirely to overseas manufacturers — 24/7 uptime required, certification extremely rigorous. CXMT also holds over 300 published patents. More critically, 4F-squared allows process node regression by one or two generations, bypassing dependence on the most advanced lithography machines.

S7 Closing (~10s)

From following the pack to crossing the finish line first, CXMT isn't grinding away at thinner walls this time — they've redesigned the house entirely. The history of memory will remember this new floor plan. I'm Peng Shu, see you next episode.

Fact Checklist (Verified, Sources: Yicai / SEMI China / Nanfang+ / Shenzhen Electronic Chamber of Commerce / Markets.com, 2026-10)

• 2026-10-10, 4th Integrated Chip and Chiplet Conference: CXMT President Cao Kanyu announced 4F² architecture progress, expected to launch next-gen DDR5 RDIMM integrating 4F² and hybrid bonding by year's end
• 4F² = cell area 4×F² (F = minimum feature size); mainstream 6F² has been in use since 2007; density improvement of 30%~50% in same area (TrendForce estimate)
• VSG (Vertical Surrounded Gate) vertical surrounding channel transistor: vertical channel + full gate wrap, solving leakage and short-channel effects
• SemiAnalysis: 4F² is the theoretical limit for single-bit cells (minimum line/space period 2F)
• Early 4F² (1980s) stalled because array and peripheral circuits were bound to the same process; CXMT's route = DRAM/CMOS decoupling + wafer-level hybrid bonding
• Over 300 published patent families; Samsung/SK Hynix targeting adoption around 2028, CXMT roughly 2 years ahead; Micron has no clear timeline
• After the news, Micron stock fell 3.9%, SK Hynix dropped about 4%
• 4F² allows feature size regression of 1~2 generations, reducing dependence on the most advanced lithography (EUV)