Huawei didn't get EUV lithography machines, so it took a different path with logic folding to create the Kirin 9050 Pro
Huawei didn't get EUV lithography machines, so it took a different path with logic folding to create the Kirin 9050 Pro. This time, Huawei dropped a technological depth charge. On July 3rd, HiSilicon CEO He Tingbo published a paper, fully disclosing the mass-production test data of the next-generation Kirin chip (codenamed Kirin 2026, likely to be commercially named the Kirin 9050 Pro). A set of numbers is absolutely staggering—transistor density has increased by...
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Huawei didn't get EUV lithography machines, so it took a different path with logic folding to create the Kirin 9050 Pro. This time, Huawei dropped a technological depth charge. On July 3rd, HiSilicon
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Huawei Didn't Get EUV Lithography Machines, So It Took a Different Path with Logic Folding to Create the Kirin 9050 Pro
Huawei just dropped a technological depth charge.
On July 3rd, HiSilicon CEO He Tingbo published a paper, fully disclosing the mass-production measured data of the next-generation Kirin chip (codenamed Kirin 2026, likely to be commercially named the Kirin 9050 Pro). A set of numbers is staggering—transistor density up 55%, power consumption down 41% at the same performance, and clock speed pushed to 3.1GHz.
But the key isn't these numbers themselves—it's the fine print behind them: All of this was achieved without changing process nodes or using EUV lithography machines.
What does "no EUV" mean? In plain English—the US choked Huawei, preventing Dutch company ASML from selling the most advanced extreme ultraviolet lithography machines to mainland China. Without this machine, making advanced chips through the traditional route was basically a dead end.
Huawei's answer this time is called LogicFolding.
What Exactly is LogicFolding?
In one sentence: "Folding" the chip.
The traditional approach in chipmaking for decades has been "geometric scaling"—continuously shrinking transistors to pack more into the same silicon area. That path has hit a wall: below 3nm, every step forward costs exponentially more.
Huawei took a different approach: keep transistor size unchanged, but stack the chip from a single planar layer into two vertically stacked layers.
How does it work? Key logic circuits go from a flat single layer to dual-layer vertical stacking, with layers connected using a technology called "hybrid bonding." This achieves:
- Wire routing distance reduced from millimeter-scale to micron-scale → signals travel faster
- Clock buffers reduced by over 50% → dynamic power consumption slashed significantly
- Clock speed pushed from 2.75GHz to 3.10GHz
- Power consumption down 41% at the same performance
He Tingbo summarized this approach as the "Tau (τ) Law"—the core idea being: stop obsessing over size, and instead focus on "making signals run faster."
Key Numbers (Official Huawei Measured Data)
| Metric | Previous Gen | This Gen | Improvement |
|---|---|---|---|
| Transistor Density | 155 MTr/mm² | 238 MTr/mm² | +55% |
| Power at Same Performance | Baseline | -41% | -41% |
| Clock Speed | 2.75 GHz | 3.10 GHz | +12.7% |
| SRAM Frequency | Baseline | +40% | +40% |
| Clock Buffers | Baseline | Reduced 50%+ | -50% |
| Clock Skew | Baseline | -25% | -25% |
| Global Wire Length | Baseline | -30% | -30% |
Key fact: Manufacturing equipment unchanged, process node untouched. In other words—these improvements were achieved entirely through internal chip architecture innovation, with zero reliance on process upgrades.
What Does This Mean for China's Semiconductor Industry?
Looking back at the timeline from 2019 makes it clearer—
That year, Huawei was placed on the US Entity List, and the EUV lithography path was completely sealed off. Dutch company ASML, under US pressure, couldn't sell its most advanced lithography machines to mainland China. This meant that through the traditional route, mainland China's chip process was stuck at the 7nm tier, while TSMC had already pushed to 2nm. Relying solely on geometric scaling, catching up was impossible.
LogicFolding offers a third path:
- No EUV required (uses mature DUV nodes)
- No geometric scaling (transistor size unchanged)
- Relies on architecture innovation (dual-layer vertical stacking + hybrid bonding + temporal scaling)
- Pushes density and performance up hard on the same process
The market reacted fast: on May 25th, the day He Tingbo spoke in Shanghai, SMIC's stock rose 7.6%. The industry understood—if this route can achieve stable mass production, it means SMIC + Huawei can bypass the EUV blockade and keep shipping competitive products without changing process nodes.
Huawei's roadmap is also aggressive: by 2031, through multi-level evolution of LogicFolding, high-end chip density will reach the equivalent of a 1.4nm process—which is the current frontier of global advanced chip manufacturing, with TSMC planning mass production in 2028.
The Sober Voices
One thing needs to be made clear: Huawei's published data is engineering measurement, not the result of third-party independent verification.
Brady Wang, Associate Director at Counterpoint Research, gave a relatively measured assessment: "In the short term, China may narrow the gap with international leaders, but at the most advanced process nodes, the technology gap will still exist."
He Hui, Head of Semiconductor Research at Omdia, pointed out a real engineering challenge: LogicFolding falls under 3D IC (three-dimensional integrated circuits), and the heat dissipation issues from multi-layer stacking are a new engineering hurdle—the thermal path for lower stacked layers naturally becomes longer, heat density rises, and this is a recognized pain point across the 3D IC industry.
There are also several open questions that can only be answered when real devices ship at year-end: - Can the yield rate for dual-layer stacking remain stable? - Hybrid bonding equipment is expensive—can costs be brought down to a range acceptable for consumer electronics? - Are design toolchains, IP libraries, and EDA tools adapted to dual-layer stacked architectures?
Three Companies, Three Paths
Zooming out—LogicFolding isn't just Huawei's story; it represents the divergence of routes in the global semiconductor industry's post-Moore era:
| Company | Route | Core Action |
|---|---|---|
| Apple / TSMC | Process leadership | TSMC N2, getting 2nm chips done |
| Intel | Process comeback + IDM 2.0 | Intel 18A, reclaiming foundry business |
| Huawei | Architecture innovation | LogicFolding + Tau Law, bypassing the EUV blockade |
Three companies, three completely different paths—no one is right or wrong; it's about who can execute.
What This Actually Means for Ordinary People
If you don't care about technical details and just want to know "what does this have to do with me":
- This fall (September-October), the Huawei Mate 90 series will debut with the Kirin 9050 Pro
- 41% lower power consumption at the same performance—better battery life
- 3.1GHz clock speed + 40% higher SRAM frequency—stronger on-device AI capabilities
- The foldable flagship Mate XT 2 / Mate X8 will also carry this chip
Final Thoughts
Huawei has delivered a smarter answer than "desperately chasing TSMC": stop chasing, switch lanes.
This isn't an emotional narrative of "we'll fight it out"—it's a real engineering breakthrough: using smarter chip design to make better products on the same or even more mature processes. Whether this path truly works will only be known when products hit the market at year-end and real devices are tested.
But at least the thinking is right. In the post-Moore era, the ceiling for architecture innovation is far from reached.
You can make great chips without EUV. That's the core of Huawei's heavyweight punch.
Written by our editorial team; tools listed here are tested or verified against public sources. Links point to official sites or GitHub repos for reference only — no paid placements.
