HBM prices are skyrocketing, forcing AMD to unveil its first "memory-package" chip — Versal Gen 2 arrives with 288GB/s bandwidth

Headline: HBM price surge pushes AMD to debut its first packaged-memory SoC, Versal Gen 2 is here

HBM (High Bandwidth Memory) prices have climbed to a point where AMD has no choice but to "forge a new path."

And the first shot has been fired at

💡 What You Will Learn

HBM prices are skyrocketing, forcing AMD to unveil its first "memory-package" chip — Versal Gen 2 arrives with 288GB/s bandwidth Headline: HBM price surge pushes AMD to debut its first packaged-memor

📜 Table of Contents

• Why "Forced"?
• Not Just Saving Memory — The Whole Board Shrinks by 60%
• 10x Compute Improvement, PCIe 6.0 and CXL 3.1 Support
• Will This Design Philosophy Get Replicated Across More Product Lines, Like Lunar Lake?
• Personal Take: What the Shortage Forced Could Be the Direction for the Next Decade
• When Can You Get It?

HBM Prices Go Crazy, AMD Forced Into Its First "Memory-on-Package" Chip — Versal Gen 2 Arrives with 288GB/s Bandwidth

Release headline: HBM price surge forces AMD's first on-package memory SoC, Versal Gen 2 is here

HBM (High Bandwidth Memory) prices have risen to the point where AMD has no choice but to "find a new path."

And the first shot has been fired on the Versal line.

AMD just announced Versal Premium Gen 2 — their first SoC featuring a Memory-on-Package (MoP) solution. It's no exaggeration to say the design implications this carries for the chip design community may be bigger than the product itself.

Why "Forced"?

Let's look at the broader industry context first.

If you've been a hardware engineer working on AI inference, network acceleration, or video processing over the past few years, you know the HBM price rollercoaster all too well. After the AI boom, HBM got bid up to astronomical prices by NVIDIA and the major cloud providers — data center demand ate up the capacity, and prices kept climbing.

AMD's Versal line has always been an Adaptive SoC (essentially FPGA + CPU + AI Engine combined), widely used in 5G base stations, network security, industrial control, AI inference, aerospace, and more. These use cases don't have unlimited budgets like data centers do — HBM price hikes hit them directly.

What's even more critical: HBM's supply chain cycle is completely tied to data centers — fast product iterations, short lifecycles. But the typical requirement for industrial/military customers is "one chip must last 10-15 years" — HBM's refresh cadence simply doesn't line up.

So AMD's decision chain is actually quite clear: you can't put all your eggs in the HBM basket.

Enter Versal Premium Gen 2, which switches to LPDDR5X on-package memory — integrating up to 4 LPDDR5X dies directly into the chip package, with a maximum capacity of 32GB, running at 9000 MT/s, delivering 288 GB/s of total bandwidth.

What level is that number? In terms of raw bandwidth, it's roughly on par with mid-range GDDR6 — but the bigger deal is it doesn't require separate memory PCB routing, and you don't need to buy HBM dies at all.

Not Just Saving Memory — The Whole Board Shrinks by 60%

Here's a set of numbers that's easy to overlook but has a massive real-world impact:

The MoP solution reduces total PCB area by over 60%.

What does that mean? Previously, when you designed a board with a Versal chip, the HBM or external LPDDR5X dies would eat up a large chunk of PCB real estate, and you'd need dedicated high-frequency signal routing simulation and validation — one mistake and you're "re-spinning the board" — and each spin costs anywhere from tens of thousands to hundreds of thousands of dollars.

Now AMD has the LPDDR5X pre-configured right in the package. The high-speed interface simulation and validation are already done at the factory — when you receive the chip, the memory is ready to go.

The benefits are immediate:

• Dramatically shorter development cycles — no more months spent on memory simulation and PCB validation
• Board-level design risk drops to zero — just handle power delivery and the physical interface
• New form factors become possible — like EDSFF (enterprise and server standard form factor) and 3U VPX (ruggedized military systems), both of which are extremely demanding on PCB area. With external memory, these were nearly impossible before; now they're a viable option.

For engineering teams building 5G base stations and ruggedized military systems, this chip could directly solve design pain points they've been wrestling with for two or three years.

10x Compute Improvement, PCIe 6.0 and CXL 3.1 Support

MoP isn't the only selling point.

AMD claims Versal Gen 2 delivers a 10x compute performance improvement over Gen 1. That number obviously depends on the specific workload, but on the key interfaces, they've gone straight to top-tier specs:

• PCIe 6.0 hard IP (64 Gb/s per lane, with Integrity and Data Encryption protection)
• CXL 3.1 support — works with AMD EPYC processors for memory pooling and expansion

The IDE (Integrity and Data Encryption) feature on PCIe 6.0 is worth calling out: it provides link-layer encryption for data in transit, preventing physical-layer data leakage. This is increasingly important in network infrastructure and data center interconnect scenarios.

Additionally, AMD has built in a 400G high-speed encryption engine — you can run high-bandwidth encryption/decryption without consuming programmable logic resources. For telecom and defense customers, this is genuinely "out-of-the-box, compliance-ready."

Temperature range is covered too: an industrial-grade wide-temperature design spanning -40°C to 110°C.

Will This Design Philosophy Get Replicated Across More Product Lines, Like Lunar Lake?

This is the most interesting question in this entire article.

The Versal line is based on Arm IP — not AMD's mainstream x86 products. But the MoP approach — putting memory into the package — last sparked widespread discussion in the x86 world with Intel's Lunar Lake.

Lunar Lake is Intel putting LPDDR5X directly into the CPU package, eliminating external memory modules. It was controversial at the time: some said "they've welded the upgrade path shut," while others argued "the power and space advantages from integration are priceless."

AMD taking the same path with Versal signals this: even when HBM isn't in shortage, MoP's technical advantages in certain scenarios are real and tangible.

288 GB/s of bandwidth + zero memory signal design risk + 60% PCB area reduction — put those three together, and for compact edge devices, ruggedized military systems, and integrated telecom equipment, this is inherently a more attractive proposition than "HBM 2e."

The HBM shortage is the catalyst, not the root cause. The root cause is: MoP is simply the more sound engineering choice in certain scenarios.

Personal Take: What the Shortage Forced Could Be the Direction for the Next Decade

This brings me to two observations.

First, Versal Gen 2's MoP design is very likely to be replicated across AMD's x86 product line.

AMD currently has no on-package memory chip on its client roadmap (aside from 3D V-Cache), but Versal's successful validation — especially in enterprise temperature ranges and market longevity — gives AMD's x86 SoC team a powerful reference point.

Intel Lunar Lake walked one path; AMD Versal Gen 2 walks another. Both paths ultimately point in the same direction: memory is shifting from a "board-level component" to a "package-level component."

Second, HBM's pricing power monopoly is being challenged.

NVIDIA has built a massive memory moat on HBM — GDDR can't deliver the bandwidth, and NVIDIA has locked up most of the HBM capacity. When AMD comes out with a 288 GB/s LPDDR5X MoP solution saying "this can run AI inference too," they're essentially offering small and mid-sized businesses and industrial users an alternative that doesn't require fighting over HBM allocations.

288 GB/s certainly isn't enough for training, but for AI inference, edge computing, and video analytics — it might be more than enough than you'd think.

When Can You Get It?

AMD's timeline:

• End of 2026: sampling begins
• Second half of 2027: mass production and shipping

In other words, in as little as a year and a half, your 5G base station, network equipment, or defense electronics could be running an AMD chip with memory built right into the package.

Let's discuss in the comments: do you think "on-package memory" will become the standard for SoCs over the next decade, or is it just a stopgap response to the HBM shortage?